1. Field of Invention
This invention relates generally to microminiature electronic circuitry, particularly to the interconnection of integrated circuit chips in a microcircuit package for permanent interconnection or testing purposes.
2. Description of the Prior Art
In high density VLSI systems, interconnection of chips is accomplished by mounting integrated circuit chips on dielectric substrates (e.g. multilayered ceramic substrates) wherein the integrated chips are electrically interconnected by wiring means such as tabs, wire bonds or arrays of solder balls such as described in U.S. Pat. No. 3,495,133, "Controlled Collapse Chip Connections", hereafter referred to as C-4's.
Even though the C-4 approach is currently used in many VLSI systems today and is rapidly becoming more widely used throughout the industry, as it has many advantages such as the facilitation of a high number of connections in a small area and self alignment of the connections with corresponding contact pads on a substrate due to the surface tension during solder reflow, there are concerns with such systems. Primarily because of the thermal coefficient of expansion (TCE) mismatch between integrated circuit chips and the dielectric substrate that they are mounted on (e.g. ceramic), there are stress problems wherein the solder joints furthest from the center of the chip experience stresses that lead to cracking as documented in "Reliability of Controlled Collapse Interconnections" by K. C. Norris and A. H. Landzberg in the IBM Journal of Research and Development, 13 (3), 266 (1969). Because of this basic problem, and the trend in the industry to make larger and more fully integrated chips, the size of chips has been limited in many instances and the circuitry of larger chips is sometimes required to overhang the connecting solder ball arrays because of the limitations that the size of the solder ball arrays can be made to due to the TCE mismatch problem. For mechanical reasons, this overhang is very limited and thus chip size is still correspondingly limited. In addition, solder ball bonding of chips to substrates does not result in chips which have top surfaces which are all planar to each other. In multi-chip modules (many state of the art modules having greater than 100 chips), this causes cooling problems because the resultant non-planarity of the chips makes it difficult for internal cooling means (e.g. pistons and the like as described in U.S. Pat. 3,993,123) to contact each chip in the same manner, making the contact area between chips and internal cooling means different for each chip. For high powered chips, this presents a complex cooling problem wherein mechanically compliant mechanisms (which are relatively poor thermal conductors), must frequently be placed between the chips and internal cooling means.
Given the increasing complexity of multi-chip modules and increased integration level of integrated circuit chips, rework of modules by replacing defective chips is economically necessary. Thus, it is desirable that removal and replacement of chips be as simple as possible, preferably without requiring solder bonds or wire bonds and their associated processing steps.
To alleviate many of the problems associated with C-4 or solder ball type systems while achieving a high density of electrical connections, it is desirable to have a flexible connection between integrated circuit chips and the package that they are electrically interconnected and mechanically mounted on. In most microcircuit applications, the forces applied by the connector must be small so that the fragile chips are not unduly stressed by connector forces. Moreover, contact wipe should be automatic because surface films and debris must be penetrated to minimize contact resistance, and at such high densities, it is not possible to guarantee the wipe of each contact by external means. In addition, alignment should be relatively simple so as to approach the self alignment that exists in solder ball or C-4 type connection systems (wherein solder reflow causes self alignment of the chips).
In addition to using area arrays of contacts for permanently connecting chips to substrates, semiconductor chips are tested through the area arrays of contacts prior to connecting the chips to the substrate. It is most common that chips be tested prior to dicing, i.e. while still in wafer form. The state of the art means for carrying out comprehensive functional testing of chips while still part of an undiced wafer incorporates "buckling beam" springs as a probe to make contact with the chip input/output pads, e.g. see IBM TDB by L. H. Faure, "Contact Probe Assembly with a Retractable Shorting Center", Vol. 19, No. 4, September 1976, pp. 1267-1268.
In a typical testing apparatus and process, an undiced wafer is held in place on a chuck (e.g. a vacuum chuck), which is mounted on a high precision X-Y table. To test a chip area of the undiced wafer, the X-Y table moves the chip area under a probe (e.g. buckling beam probe) so that the chip is accurately aligned with the probe. The probe is then lowered onto the chip, while certain contact positions are monitored for initial contact. After initial contact occurs, the probe is lowered a nominal amount determined by experiment with a particular probe (e.g. 0.002 inches) to complete the temporary contact. The probes are densely populated with over 600 buckling beam spring contacts. Each buckling beam spring is essentially a flat strip with some curvature to it (e.g. see above referenced IBM TDB by Faure), and being approximately 0.25 inches long. As the buckling beam springs contact state of the art solder ball chip contacts, they deform somewhat and penetrate the solder or contact pad, to assure electrical contact.
As the amount of chip input/output, hereinafter referred to as I/O, increase, the buckling beam approach has become limited in high density, high performance applications. Electrical reasons for such limitations are that the relatively long spring length adds inductance which cannot be tolerated with today's chips having increased speed, and that mutual coupling occurs due to the dense amount of ccntacts in parallel. Mechanically, the state of the art in fabrication of the buckling beam springs is limited, and chip densities are increasing at a rate that buckling beam springs are at their limit in many applications, and have already been surpassed in some state of the art applications. Thus, there is also a need in the art for a dense test probe which can make temporary connections to the I/O or solder balls, (if a solder ball or C-4 system is used for permanent chip connections in a certain instance), attached to a chip, while providing low inductance, positive mechanical contact, and automatic wipe.
There have been known several types of flexible or elastomeric interconnection means in the art. For example, U.S. Pat. No. 3,683,105 teaches the use of multilayers of conductors fabricated on a dielectric film to integrate integrated circuit chips on a multilayer, multichip substrate. This patent is successful at providing an interconnection path between pads on integrated circuit chips and conductors on the top surface of an underlying substrate. However, the density is limited for chips having arrays of I/O pads such as C-4 pads because there is not a direct path between chip I/O pads beneath the chips and ceramic substrate I/O pads, but instead the path comprises metal lines which are approximately as long as the chip width running along the top and bottom of a dielectric film. These lines must pass the chip perimeter in order to connect to the next level of packaging by vias made in the underlying film. It is also not possible to have direct through connections because connection of the substrate to the dielectric film requires thermocompressive bonding after chip attachment to the film. Thus, connecting lines cannot exist under the chips, because one cannot form thermocompression bonds through the chips.
U.S. Pat. No. 4,008,300 discloses a multiconductor element for interconnecting printed circuit boards and the like. Conductive material consisting of a slurry of a conductive powder in a liquid vehicle is filled into gaps created in an elastomeric material, with the conductive material protruding above the surface of the elastomeric base material. The conductive powder conductors in this interconnection means are limited in electrical performance because their maximum conductivity is much less (i.e., approximately by a factor of 100) than corresponding solid metals such as copper or gold. Conductive powders cannot support the required current of approximately 250 mA/contact for certain power feed through locations (approximately 4 mil diameter per contact) required in VLSI applications. In present VLSI applications, approximately one third of the total number of feedthroughs are power feedthroughs. In addition, connectors used for connecting chips to substrates require that wipe between contacts be guaranteed for each connection so that accumulated films and debris between contacts are penetrated so that positive metal to metal contact occurs, and so that contact resistance is not unduly high. There is no means for automatic wipe in 4,008,300.
U.S. Pat. No. 4,003,621 discloses an electrical connector having a plurality of electrically conductive linear elements in an elastomer material. The connector is not well suited for connecting chips having a dense area array of contacts, or for testing such chips primarily because there is no allowance for wiping between aligned contacts. As stated above, it is desirable to have automatic wipe in a dense interconnection system. The failure of a single chip connection to make proper contact can be catastrophic for a system having thousands of chip interconnnections. The solid through conductors of 4,003,621 must be deformed to make proper contact. Accordingly, flexible contact wherein connectors are reuseable is not possible because deformation of entire non-flexible conductive elements is required. Since the conductive element is itself neither flexible nor resilient, use of this connector to connect chips more than once is essentially not possible.
U.S. Pat. No. 3,967,162 discloses a flexible connector wherein a flexible sheet has a plurality of paired contacts formed thereon in predetermined positions, with wiring strips electrically connecting each pair of contacts and the flexible sheet biasing the contacts into engagement. The density would be limited if used for connecting VLSI chips having area arrays of I/O pads because the conductors do not go through the elastomer body, but run along the top, bottom and sides of the flexible sheet. This long path would also present electrical concerns in high performance VLSI packages.
U.S. Pat. No. 4,330,165 discloses a means for interconnecting the contacts of two circuit boards wherein a plurality of linear conductors are embedded in an elastomer. As in the 4,003,621 reference, there are no provisions for automatic wipe, and it is not suited for dense chip to substrate connections or testing of area array chips. The metal conductors do not provide a flexible reusable connection system because they are only deformable, not flexible and resilient, even though they exist in an elastomer matrix. Use of this system requires a deformation of the metal conductors, thus use of this connector to connect chips more than once is essentially not possible.
U.S. Pat. No. 4,548,451 discloses an elastomeric connector interposer for connecting modules and printed circuit boards. The elastomeric connector disclosed therein cannot be utilized for connecting the contacts of dense area array chips to a substrate because of inherent I/O density limitations, and because of alignment problems. The state of the art area array chips that must either be connected or tested presently have I/O contacts on pitches between 8 and 12 mils, and the trend is to reduce this so that chips in the near future can be expected to have their I/O on a pitch as low as 6 mils. The subcomponents required for the '451 patent are through-vias 18 (which must have a conductor therein, and be at least approximately 4 mils in diameter to carry the current required for the power I/O locations of the chip); flexible appendages 20 which extend from flexible overlay 15 which is bonded to resilient base member 10; and the free end of appendages 20 lying above deformable protrusions 9. All of these subcomponents are required to achieve contact and wipe, and to use that connector on chips wherein a 4 mil minimum through-hole is required to carry the requisite current, then the minimum pitch possible would be in the 25 mil range which is unsuitable for the state of the art area array chips which require a denser I/O array than 25 mil spacings can provide. Alignment is critical in elastomeric chip connectors whereas it is not critical in solder ball connections which are self aligning. If used in a chip connection or test application, the contact area for alignment in the '451 patent, i.e. contact point 17, does not facilitate easy alignment primarily because of the relatively small target area which is a fundamental part of that connector because it contributes to allowing pressure contact with a minimum force, and is an interdependent subcomponent with the other portions of that connector structure.
U.S. Pat. No. 4,402,562 also discloses a means for interconnecting printed circuit: boards wherein an elastic material having aniostropical electroconductivity and two insulating holder members. Electrical performance is limited because the conductors are not solid metal but an elastic-type composite of alternating insulators and conductors such as conductor filled resins.
In view of the above requirements for an elastomer connector for mounting and electrically connecting area array VLSI chips to substrates or temporarily connecting area array VLSI chips to a test probe and the existing elastomer connector art, it is evident that there is a need for an elastomeric connector which is capable of interconnecting high density VLSI chips having area array contacts. There is also a need that the elastomeric connector provide a short, direct, low inductance electrical path between corresponding contacts of the VLSI chips and substrate or test probe being connected thereto; and that flexibility be such that minimal forces are exerted upon the chips and sufficient compliance exists so that chips mounted on substrates may be planar to each other so that thermal enhancements required for dissipating heat from high powered VLSI chips will contact the chips evenly, and mechanically flexible mechanisms will be eliminated, thus reducing thermal resistance. There is a need that the connector have conductors exhibiting electrical conductivity equivalent to solid metals such as Cu, and Ag, etc. so that the connectors have low resistivity to support high currents of up to approximately 250 mA for a via of approximately 4 mils (i.e. approximately 20 mA/square mil) over long periods of time for certain power feedthrough locations. Note that the current densities for some signal feedthrough locations are an order of magnitude less than this requirement (i.e. approx. 2 mA/square mil). The connector must provide automatic wiping action and be capable of having chips attached and detached thereto by inherent mechanical means only, without requiring solder reflowing.